Job Description

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The Role

Were searching for a Senior/Staff Analog Design Engineer to architect, design and bring to production ultrahighspeed (> 20 GHz analog bandwidth, > 40 GS/s) CMOS ADCs and DACs that directly interface with our optical compute fabric. Success in this role requires mastery of lowjitter sampling circuits, broadband front ends, and calibration techniques that deliver outstanding ENOB and power efficiency. The ideal candidate will have a strong background in electrical engineering and semiconductor physics, along with a passion for developing reliable, highperformance analogue circuits that drive breakthrough AI hardware.

Responsibilities

• Define converter architectures that will deliver on the target of Analog bandwidth > 20 GHz.
• Design critical highspeed building blocks: bootstrapped or switchlinearised T/H, lowskew clock trees (< 50 fs rms aperture jitter), broadband input buffers, thermometer and binaryweighted current cells, dynamic element matching (DEM) and background calibration loops.
• Model and close performance using transistorlevel and behavioural cosimulation (SpectreRF / AFS RF + VerilogA/AMS), then drive postlayout extraction, EM/IR and thermal analysis to achieve firstsilicon success.
• Collaborate with packaging, SerDes and PLL teams to codesign I/O impedance, ESD, supply isolation and oninterposer routing so converters integrate cleanly into multilane fabrics.
• Lead silicon bringup: onwafer static and dynamic tests, highspeed digitiser / AWG measurements, DNL/INL, staticpower and jitter transfer characterisation; oversee production test pattern generation and builtin selftest (BIST) hooks.
• Mentor junior engineers, conduct rigorous design and layout reviews, and publish internal appnotes to disseminate best practices for GHzclass dataconverter design.
• Track and inject into the team the latest advances in timeinterleaving calibration, background mismatch correction, supplynoise tolerant reference generation and layout techniques.

Skills & Experience

• 7 + years of production CMOS dataconverter design, with at least two tapeouts running 20 GHz analog bandwidth.
• Deep knowledge of trackandhold linearity, aperturejitter minimisation, currentsteering DAC glitch energy reduction, capacitor and device matching, and metastabilityhard comparators.
• Proficiency with industry EDA flows: Cadence Virtuoso, SpectreRF / AFS RF, VerilogA/AMS, EMX / HFSS for package + onchip inductor modelling, and mixedsignal verification.
• Demonstrated ability to achieve < 100 fs rms aperture jitter, < 0.5 LSB DNL/INL (postcalibration), and lowppm clocktodata skew in silicon.
• Experience incorporating digital calibration engines (DSP or controllerdriven) for offset, gain, timing and elementmismatch correction.
• Solid grasp of supplynoise coupling, substrate isolation, ESD, latchup, and advancednode layout techniques (double patterning, EUV constraints, local interconnect).
• Strong lab skills: highspeed AWG/BERT operation, FFTbased dynamic testing, deembedding, and scripting (Python / MATLAB) for data reduction.
• Bachelors degree in Electrical Engineering or related field (Masters / PhD preferred).
• Excellent communication, crossdisciplinary collaboration, and a demonstrated ability to execute quickly in innovationdriven environments.

Compensation & Benefits

• $194,000 $270,000, depending on experience, skills, and location.
• Competitive stock options, youre not just part of the journey, you will own a piece of it.
• Live within 45 minutes of the office? Perfect. Live within 20 minutes? Well add an extra location bonus to your salary.
• We offer financial and operational relocation support (US and abroad), through a dedicated thirdparty provider who is on hand to make your move as seamless as possible.
• We offer visa sponsorship so if we make you an offer we will make every reasonable effort to secure you a visa, but we may not be able to sponsor visas for every role and candidate.
• Were in the process of setting up a US group policy once we have 5+ employees. In the meantime, were providing a health insurance stipend of $800/month to offset costs. Once the group policy is live, Flux will cover 100% of the employee premium, and offer options like dental, vision and life insurance with an aim to remain competitive among Austin tech and start up employers.
• We offer US employees access to a 401(k) retirement savings plan and we plan to introduce an employer match in line with tech market norms (commonly in the 4-5% range). Our goal is to keep our retirement benefits competitive while we scale.
• Top of the line, high-spec tech for everyone.
• Sony noisecancelling headphones and ergonomic setups to keep you comfortable and focused.
• Personal company card to spend on tools that help you do your job - like ChatGPT Pro or anything else that boosts your workflow.
• Periodic travel to London HQ and regular team socials.
• 33 days of paid time off (PTO), including US federal holidays.

Due to U.S. export control regulations, candidates eligibility to work at Flux depends on their most recent citizenship or permanent residency status. We are generally unable to consider applicants whose most recent citizenship or permanent residence is in certain restricted countries (currently including Iran, North Korea, Syria, Cuba, Russia, Belarus, China, Hong Kong, Macau, and Venezuela). Applicants who have subsequently obtained citizenship or permanent residency in another country not subject to these restrictions may still be eligible.

We do not accept unsolicited CVs from recruitment agencies, will not be liable for any fees, and prohibit unauthorised use of our company name in recruitment activities.

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Seniority level

MidSenior level

Employment type

Fulltime

Job function

Engineering and Information Technology

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